Few electronic components have received as much engineering attention as dynamic random access memory (DRAM) cells. The most commonly used memory cell is the one transistor-one capacitor type. The transistor, called a transfer transistor, controls current to and from a bit line attached to the drain of the transistor. Usually, a five volt charge is placed across the capacitor to represent a one and a zero volt charge is placed across the capacitor to represent a zero. Data is read from the memory cell by turning on the transfer transistor and determining the charge stored on the capacitor. The sophisticated applications available in many digital devices, such as microcomputers, creates a high demand on memory capacity. This creates intense pressure to pack as much memory capacity onto a single chip as possible. Enormous amounts of engineering talent and time have been applied to the task of reducing the size of memory cells so as to provide a greater number of cells on a single chip. One such type of memory cell is the trench capacitor cell.
In the trench capacitor cell, a transistor is formed in the surface of the major face of a semiconductor substrate. This transistor controls current to a capacitor which is formed in some manner in or surrounding a trench etched into the major face of the substrate. By forming the capacitor around the trench, a much greater capacitance value may be attained in a given surface area of the major face of the substrate. Examples of such memory cells in the prior art are Baglee, et al., U.S. Pat. No. 4,721,987, issued Jan. 26, 1988 and assigned to the assignee of this application, Kuo, No. 4,225,945, issued Sep. 30, 1980 and assigned to the assignee of the application and Japan Kokai No. 51-130178, published Dec. 11, 1976.
The trench capacitor memory cells do substantially decrease the surface area of memory cells. However, these types of memory cells introduce complexities which cause poor yield and increased expense of manufacture. In addition, although the memory cells themselves have been shrunk using the prior art trench transistor concepts, the isolation area between memory cells still occupies a substantial mount of substrate surface area.